The subject matter disclosed herein relates to integrated circuit devices. More particularly, the subject matter relates to capacitor structures in three-dimensional (3D) integrated circuit (IC) structures.
Monolithic 3D structures are built with multiple transistors stacked on top of one another, in what is sometimes referred to as a sequential fabrication process. These structures include fabricated connections which are significantly smaller than the through-silicon vias (TSVs) used to vertically connect transistors in conventional IC structures. However, due to minimal spacing between circuit components in these monolithic 3D structures, controlling manufacturing yield and limiting undesirable boundary effects can create design challenges.